Data Structures

Here are the data structures with brief descriptions:
clockConfigurationThe internal hardware parameters associated with a given CPU clock speed
FacePrinterA FacePrinter is capable of performing low-level printing operations to some assigned (physical or 'virtual') face
fioparmsAn AVRDUDE struct describing the ways in which a file may be opened
GPIOInterruptHandlerInfoInformation about an external interrupt handler attached to a GPIO pin
GRLA GRL is a "General Reflex Locator"
ihexrecThe description of a single line of an Intel "ihex" format "hex file"
PacketHeaderThe information associated with a packet, when it is stored in memory only -- there is no preestablished packet header on the wire
PacketPrinterHeaderStores the information needed to use a virtual face to print a packet into a user-supplied buffer
PinInfo_sA description of a single SFB-programmer-visible hardware pin
ProgrammerA structure holding state associated with a program we may burn or are in the process of burning
PWMInfoThe per-PWM-capable SFB pin information needed to configure PWM on that pin
SDRawA class to control an SD Card
SDRawDiskInfoInformation associated with an SD Card
SFB_CONFIG_MEM_TThe data stored in flash configuration memory by the SFB _secondary_ bootloader
SFBAlarmManage "alarm clock"-style settable timers
SFBBootBlockThe exactly-64-byte-long SFB 'boot block' contents
SFBBrainReflexA 'convenience class' (with a prebuilt instance Brain) which provides a means of declaring reflexes that trigger at the "brain" -- i.e., after the individual faces and the Spine
SFBByteBufferBase class providing services common to SFBRxByteBuffer and SFBTxByteBuffer
SFBDispatchEntryAn SFBDispatchEntry describes an SFB reflex
SFBEepromWrapper class implementing the EEPROM object for access to the EEPROM
SFBFrameHandles packet framing and deframing
SFBGRLMasterTableThe description of all the known arrays-of-PacketHandler's 'reflex tables'
SFBHeapA minimal heap memory allocator, based on the ancient K&R approach
SFBHWHostRegisterAn incomplete cut at host-side simulation of the SFB hardware registers
SFBHWI2CProvide access to the I2C bus hardware on the IXM
SFBHWSerialThe object supporting 'hardware level' serial operations on the SFB
SFBHWTimerThe representation of a hardware timer
SFBMemoryA class for temporarily storing packets, and then retriggering on them at a later time
SFBNetClass supporting 'service gradient routing' via the Net
SFBProcessorWrapper class implementing the Processor object for access to CPU speed control
SFBProfileA profiling system providing millisecond resolution for over a month's worth of runtime
SFBProvenanceAn SFBProvenance provides information that describes a sketch as a physical artifact
SFBQLEDA simple queuing system to allow displaying various 'blink patterns' on the SFB built-in LEDs without having to block
SFBReactorThe SFBReactor manages the SFB reflex triggering system: It determines how an SFB will react to any given packet type
SFBRxByteBufferA specialized SFBByteBuffer that handles asynchronous data reception, i.e., data is added to the buffer at interrupt level (IL), and removed from the buffer in the background process (BG)
SFBSerialA serial communications "endpoint", implementing the SFB packet protocol, including baud rate negotiation (BRN)
SFBSpineReflexA 'convenience class' (with a prebuilt instance Spine) which provides a means of declaring reflexes that trigger at the "spine" -- i.e., after the individual faces, but before the Brain
SFBTickerThe short-term, high-resolution profiling information maintained by the core
SFBTxByteBufferA specialized SFBByteBuffer that handles asynchronous data transmission, i.e., data is added to the buffer in the background process (BG), and removed from the buffer at interrupt level (IL)
UartDescriptorUART (hardware serial port) configuration information

Generated on Fri Apr 22 06:57:07 2011 for SFB by doxygen 1.5.9