LPC23xx.h

00001 /******************************************************************************
00002  *   LPC23xx.h:  Header file for NXP LPC23xx/24xx Family Microprocessors
00003  *   The header file is the super set of all hardware definition of the
00004  *   peripherals for the LPC23xx/24xx family microprocessor.
00005  *
00006  *   Copyright(C) 2006, NXP Semiconductor
00007  *   All rights reserved.
00008  *
00009  *   History
00010  *   2005.10.01  ver 1.00    Prelimnary version, first Release
00011  *
00012  ******************************************************************************/
00013 
00014 /* Modified by Martin Thomas */
00015 /* Modified by David Ackley - generic UART offsets */
00016 
00017 #ifdef HOST_MODE
00018 #error "LPC23xx.h must not be included in HOST_MODE"
00019 #endif
00020 
00021 #ifndef __LPC23xx_H
00022 #define __LPC23xx_H
00023 
00024 /* Vectored Interrupt Controller (VIC) */
00025 #define VIC_BASE_ADDR   0xFFFFF000
00026 #define VICIRQStatus   (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x000))
00027 #define VICFIQStatus   (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x004))
00028 #define VICRawIntr     (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x008))
00029 #define VICIntSelect   (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x00C))
00030 #define VICIntEnable   (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x010))
00031 #define VICIntEnClr    (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x014))
00032 #define VICSoftInt     (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x018))
00033 #define VICSoftIntClr  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x01C))
00034 #define VICProtection  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x020))
00035 #define VICSWPrioMask  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x024))
00036 
00037 #define VICVectAddr0   (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x100))
00038 #define VICVectAddr1   (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x104))
00039 #define VICVectAddr2   (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x108))
00040 #define VICVectAddr3   (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x10C))
00041 #define VICVectAddr4   (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x110))
00042 #define VICVectAddr5   (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x114))
00043 #define VICVectAddr6   (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x118))
00044 #define VICVectAddr7   (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x11C))
00045 #define VICVectAddr8   (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x120))
00046 #define VICVectAddr9   (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x124))
00047 #define VICVectAddr10  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x128))
00048 #define VICVectAddr11  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x12C))
00049 #define VICVectAddr12  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x130))
00050 #define VICVectAddr13  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x134))
00051 #define VICVectAddr14  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x138))
00052 #define VICVectAddr15  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x13C))
00053 #define VICVectAddr16  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x140))
00054 #define VICVectAddr17  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x144))
00055 #define VICVectAddr18  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x148))
00056 #define VICVectAddr19  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x14C))
00057 #define VICVectAddr20  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x150))
00058 #define VICVectAddr21  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x154))
00059 #define VICVectAddr22  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x158))
00060 #define VICVectAddr23  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x15C))
00061 #define VICVectAddr24  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x160))
00062 #define VICVectAddr25  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x164))
00063 #define VICVectAddr26  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x168))
00064 #define VICVectAddr27  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x16C))
00065 #define VICVectAddr28  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x170))
00066 #define VICVectAddr29  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x174))
00067 #define VICVectAddr30  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x178))
00068 #define VICVectAddr31  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x17C))
00069 
00070 /* The name convention below is from previous LPC2000 family MCUs, in LPC23xx/24xx,
00071 these registers are known as "VICVectPriority(x)". */
00072 #define VICVectCntl0   (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x200))
00073 #define VICVectCntl1   (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x204))
00074 #define VICVectCntl2   (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x208))
00075 #define VICVectCntl3   (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x20C))
00076 #define VICVectCntl4   (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x210))
00077 #define VICVectCntl5   (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x214))
00078 #define VICVectCntl6   (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x218))
00079 #define VICVectCntl7   (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x21C))
00080 #define VICVectCntl8   (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x220))
00081 #define VICVectCntl9   (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x224))
00082 #define VICVectCntl10  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x228))
00083 #define VICVectCntl11  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x22C))
00084 #define VICVectCntl12  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x230))
00085 #define VICVectCntl13  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x234))
00086 #define VICVectCntl14  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x238))
00087 #define VICVectCntl15  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x23C))
00088 #define VICVectCntl16  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x240))
00089 #define VICVectCntl17  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x244))
00090 #define VICVectCntl18  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x248))
00091 #define VICVectCntl19  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x24C))
00092 #define VICVectCntl20  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x250))
00093 #define VICVectCntl21  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x254))
00094 #define VICVectCntl22  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x258))
00095 #define VICVectCntl23  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x25C))
00096 #define VICVectCntl24  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x260))
00097 #define VICVectCntl25  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x264))
00098 #define VICVectCntl26  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x268))
00099 #define VICVectCntl27  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x26C))
00100 #define VICVectCntl28  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x270))
00101 #define VICVectCntl29  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x274))
00102 #define VICVectCntl30  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x278))
00103 #define VICVectCntl31  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x27C))
00104 
00105 /* mthomas - added "real" names */
00106 #define VICVectPriority0   (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x200))
00107 #define VICVectPriority1   (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x204))
00108 #define VICVectPriority2   (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x208))
00109 #define VICVectPriority3   (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x20C))
00110 #define VICVectPriority4   (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x210))
00111 #define VICVectPriority5   (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x214))
00112 #define VICVectPriority6   (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x218))
00113 #define VICVectPriority7   (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x21C))
00114 #define VICVectPriority8   (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x220))
00115 #define VICVectPriority9   (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x224))
00116 #define VICVectPriority10  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x228))
00117 #define VICVectPriority11  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x22C))
00118 #define VICVectPriority12  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x230))
00119 #define VICVectPriority13  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x234))
00120 #define VICVectPriority14  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x238))
00121 #define VICVectPriority15  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x23C))
00122 #define VICVectPriority16  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x240))
00123 #define VICVectPriority17  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x244))
00124 #define VICVectPriority18  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x248))
00125 #define VICVectPriority19  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x24C))
00126 #define VICVectPriority20  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x250))
00127 #define VICVectPriority21  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x254))
00128 #define VICVectPriority22  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x258))
00129 #define VICVectPriority23  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x25C))
00130 #define VICVectPriority24  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x260))
00131 #define VICVectPriority25  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x264))
00132 #define VICVectPriority26  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x268))
00133 #define VICVectPriority27  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x26C))
00134 #define VICVectPriority28  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x270))
00135 #define VICVectPriority29  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x274))
00136 #define VICVectPriority30  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x278))
00137 #define VICVectPriority31  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x27C))
00138 
00139 
00140 #define VICVectAddr    (*(volatile unsigned long *)(VIC_BASE_ADDR + 0xF00))
00141 
00142 
00143 /* Pin Connect Block */
00144 #define PINSEL_BASE_ADDR        0xE002C000
00145 #define PINSEL0        (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x00))
00146 #define PINSEL1        (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x04))
00147 #define PINSEL2        (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x08))
00148 #define PINSEL3        (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x0C))
00149 #define PINSEL4        (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x10))
00150 #define PINSEL5        (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x14))
00151 #define PINSEL6        (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x18))
00152 #define PINSEL7        (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x1C))
00153 #define PINSEL8        (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x20))
00154 #define PINSEL9        (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x24))
00155 #define PINSEL10       (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x28))
00156 
00157 #define PINMODE_BASE_ADDR       (PINSEL_BASE_ADDR+0x40)
00158 #define PINMODE0        (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x40))
00159 #define PINMODE1        (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x44))
00160 #define PINMODE2        (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x48))
00161 #define PINMODE3        (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x4C))
00162 #define PINMODE4        (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x50))
00163 #define PINMODE5        (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x54))
00164 #define PINMODE6        (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x58))
00165 #define PINMODE7        (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x5C))
00166 #define PINMODE8        (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x60))
00167 #define PINMODE9        (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x64))
00168 
00169 /* General Purpose Input/Output (GPIO) */
00170 #define GPIO_BASE_ADDR          0xE0028000
00171 #define IOPIN0         (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x00))
00172 #define IOSET0         (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x04))
00173 #define IODIR0         (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x08))
00174 #define IOCLR0         (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x0C))
00175 #define IOPIN1         (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x10))
00176 #define IOSET1         (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x14))
00177 #define IODIR1         (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x18))
00178 #define IOCLR1         (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x1C))
00179 
00180 /* mthomas - alias */
00181 #define IO0PIN         (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x00))
00182 #define IO0SET         (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x04))
00183 #define IO0DIR         (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x08))
00184 #define IO0CLR         (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x0C))
00185 #define IO1PIN         (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x10))
00186 #define IO1SET         (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x14))
00187 #define IO1DIR         (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x18))
00188 #define IO1CLR         (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x1C))
00189 
00190 
00191 /* GPIO Interrupt Registers */
00192 #define IO0_INT_EN_R    (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x90))
00193 #define IO0_INT_EN_F    (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x94))
00194 #define IO0_INT_STAT_R  (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x84))
00195 #define IO0_INT_STAT_F  (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x88))
00196 #define IO0_INT_CLR     (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x8C))
00197 
00198 #define IO2_INT_EN_R    (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0xB0))
00199 #define IO2_INT_EN_F    (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0xB4))
00200 #define IO2_INT_STAT_R  (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0xA4))
00201 #define IO2_INT_STAT_F  (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0xA8))
00202 #define IO2_INT_CLR     (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0xAC))
00203 
00204 #define IO_INT_STAT     (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x80))
00205 
00206 #define PARTCFG_BASE_ADDR               0x3FFF8000
00207 #define PARTCFG        (*(volatile unsigned long *)(PARTCFG_BASE_ADDR + 0x00))
00208 
00209 /* Fast I/O setup */
00210 #define FIO_BASE_ADDR           0x3FFFC000
00211 #define FIO0DIR        (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x00))
00212 #define FIO0MASK       (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x10))
00213 #define FIO0PIN        (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x14))
00214 #define FIO0SET        (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x18))
00215 #define FIO0CLR        (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x1C))
00216 
00217 #define FIO1DIR        (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x20))
00218 #define FIO1MASK       (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x30))
00219 #define FIO1PIN        (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x34))
00220 #define FIO1SET        (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x38))
00221 #define FIO1CLR        (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x3C))
00222 
00223 #define FIO2DIR        (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x40))
00224 #define FIO2MASK       (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x50))
00225 #define FIO2PIN        (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x54))
00226 #define FIO2SET        (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x58))
00227 #define FIO2CLR        (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x5C))
00228 
00229 #define FIO3DIR        (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x60))
00230 #define FIO3MASK       (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x70))
00231 #define FIO3PIN        (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x74))
00232 #define FIO3SET        (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x78))
00233 #define FIO3CLR        (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x7C))
00234 
00235 #define FIO4DIR        (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x80))
00236 #define FIO4MASK       (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x90))
00237 #define FIO4PIN        (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x94))
00238 #define FIO4SET        (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x98))
00239 #define FIO4CLR        (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x9C))
00240 
00241 /* FIOs can be accessed through WORD, HALF-WORD or BYTE. */
00242 #define FIO0DIR0       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x00))
00243 #define FIO1DIR0       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x20))
00244 #define FIO2DIR0       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x40))
00245 #define FIO3DIR0       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x60))
00246 #define FIO4DIR0       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x80))
00247 
00248 #define FIO0DIR1       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x01))
00249 #define FIO1DIR1       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x21))
00250 #define FIO2DIR1       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x41))
00251 #define FIO3DIR1       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x61))
00252 #define FIO4DIR1       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x81))
00253 
00254 #define FIO0DIR2       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x02))
00255 #define FIO1DIR2       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x22))
00256 #define FIO2DIR2       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x42))
00257 #define FIO3DIR2       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x62))
00258 #define FIO4DIR2       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x82))
00259 
00260 #define FIO0DIR3       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x03))
00261 #define FIO1DIR3       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x23))
00262 #define FIO2DIR3       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x43))
00263 #define FIO3DIR3       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x63))
00264 #define FIO4DIR3       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x83))
00265 
00266 #define FIO0DIRL       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x00))
00267 #define FIO1DIRL       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x20))
00268 #define FIO2DIRL       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x40))
00269 #define FIO3DIRL       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x60))
00270 #define FIO4DIRL       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x80))
00271 
00272 #define FIO0DIRU       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x02))
00273 #define FIO1DIRU       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x22))
00274 #define FIO2DIRU       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x42))
00275 #define FIO3DIRU       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x62))
00276 #define FIO4DIRU       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x82))
00277 
00278 #define FIO0MASK0      (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x10))
00279 #define FIO1MASK0      (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x30))
00280 #define FIO2MASK0      (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x50))
00281 #define FIO3MASK0      (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x70))
00282 #define FIO4MASK0      (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x90))
00283 
00284 #define FIO0MASK1      (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x11))
00285 #define FIO1MASK1      (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x21))
00286 #define FIO2MASK1      (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x51))
00287 #define FIO3MASK1      (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x71))
00288 #define FIO4MASK1      (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x91))
00289 
00290 #define FIO0MASK2      (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x12))
00291 #define FIO1MASK2      (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x32))
00292 #define FIO2MASK2      (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x52))
00293 #define FIO3MASK2      (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x72))
00294 #define FIO4MASK2      (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x92))
00295 
00296 #define FIO0MASK3      (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x13))
00297 #define FIO1MASK3      (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x33))
00298 #define FIO2MASK3      (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x53))
00299 #define FIO3MASK3      (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x73))
00300 #define FIO4MASK3      (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x93))
00301 
00302 #define FIO0MASKL      (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x10))
00303 #define FIO1MASKL      (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x30))
00304 #define FIO2MASKL      (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x50))
00305 #define FIO3MASKL      (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x70))
00306 #define FIO4MASKL      (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x90))
00307 
00308 #define FIO0MASKU      (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x12))
00309 #define FIO1MASKU      (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x32))
00310 #define FIO2MASKU      (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x52))
00311 #define FIO3MASKU      (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x72))
00312 #define FIO4MASKU      (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x92))
00313 
00314 #define FIO0PIN0       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x14))
00315 #define FIO1PIN0       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x34))
00316 #define FIO2PIN0       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x54))
00317 #define FIO3PIN0       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x74))
00318 #define FIO4PIN0       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x94))
00319 
00320 #define FIO0PIN1       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x15))
00321 #define FIO1PIN1       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x25))
00322 #define FIO2PIN1       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x55))
00323 #define FIO3PIN1       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x75))
00324 #define FIO4PIN1       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x95))
00325 
00326 #define FIO0PIN2       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x16))
00327 #define FIO1PIN2       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x36))
00328 #define FIO2PIN2       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x56))
00329 #define FIO3PIN2       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x76))
00330 #define FIO4PIN2       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x96))
00331 
00332 #define FIO0PIN3       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x17))
00333 #define FIO1PIN3       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x37))
00334 #define FIO2PIN3       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x57))
00335 #define FIO3PIN3       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x77))
00336 #define FIO4PIN3       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x97))
00337 
00338 #define FIO0PINL       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x14))
00339 #define FIO1PINL       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x34))
00340 #define FIO2PINL       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x54))
00341 #define FIO3PINL       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x74))
00342 #define FIO4PINL       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x94))
00343 
00344 #define FIO0PINU       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x16))
00345 #define FIO1PINU       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x36))
00346 #define FIO2PINU       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x56))
00347 #define FIO3PINU       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x76))
00348 #define FIO4PINU       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x96))
00349 
00350 #define FIO0SET0       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x18))
00351 #define FIO1SET0       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x38))
00352 #define FIO2SET0       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x58))
00353 #define FIO3SET0       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x78))
00354 #define FIO4SET0       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x98))
00355 
00356 #define FIO0SET1       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x19))
00357 #define FIO1SET1       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x29))
00358 #define FIO2SET1       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x59))
00359 #define FIO3SET1       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x79))
00360 #define FIO4SET1       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x99))
00361 
00362 #define FIO0SET2       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1A))
00363 #define FIO1SET2       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x3A))
00364 #define FIO2SET2       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5A))
00365 #define FIO3SET2       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7A))
00366 #define FIO4SET2       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9A))
00367 
00368 #define FIO0SET3       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1B))
00369 #define FIO1SET3       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x3B))
00370 #define FIO2SET3       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5B))
00371 #define FIO3SET3       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7B))
00372 #define FIO4SET3       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9B))
00373 
00374 #define FIO0SETL       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x18))
00375 #define FIO1SETL       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x38))
00376 #define FIO2SETL       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x58))
00377 #define FIO3SETL       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x78))
00378 #define FIO4SETL       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x98))
00379 
00380 #define FIO0SETU       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x1A))
00381 #define FIO1SETU       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x3A))
00382 #define FIO2SETU       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x5A))
00383 #define FIO3SETU       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x7A))
00384 #define FIO4SETU       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x9A))
00385 
00386 #define FIO0CLR0       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1C))
00387 #define FIO1CLR0       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x3C))
00388 #define FIO2CLR0       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5C))
00389 #define FIO3CLR0       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7C))
00390 #define FIO4CLR0       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9C))
00391 
00392 #define FIO0CLR1       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1D))
00393 #define FIO1CLR1       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x2D))
00394 #define FIO2CLR1       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5D))
00395 #define FIO3CLR1       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7D))
00396 #define FIO4CLR1       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9D))
00397 
00398 #define FIO0CLR2       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1E))
00399 #define FIO1CLR2       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x3E))
00400 #define FIO2CLR2       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5E))
00401 #define FIO3CLR2       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7E))
00402 #define FIO4CLR2       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9E))
00403 
00404 #define FIO0CLR3       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1F))
00405 #define FIO1CLR3       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x3F))
00406 #define FIO2CLR3       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5F))
00407 #define FIO3CLR3       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7F))
00408 #define FIO4CLR3       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9F))
00409 
00410 #define FIO0CLRL       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x1C))
00411 #define FIO1CLRL       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x3C))
00412 #define FIO2CLRL       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x5C))
00413 #define FIO3CLRL       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x7C))
00414 #define FIO4CLRL       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x9C))
00415 
00416 #define FIO0CLRU       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x1E))
00417 #define FIO1CLRU       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x3E))
00418 #define FIO2CLRU       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x5E))
00419 #define FIO3CLRU       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x7E))
00420 #define FIO4CLRU       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x9E))
00421 
00422 /* bit 0 in SCS register, port 0/1 are regular ports when bit 0 
00423 is 0,  fast ports when bit 0 is 1. */
00424 #define GPIOM         0x00000001
00425 
00426 /* System Control Block(SCB) modules include Memory Accelerator Module,
00427 Phase Locked Loop, VPB divider, Power Control, External Interrupt,
00428 Reset, and Code Security/Debugging */
00429 #define SCB_BASE_ADDR   0xE01FC000
00430 
00431 /* Memory Accelerator Module (MAM) */
00432 #define MAMCR          (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x000))
00433 #define MAMTIM         (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x004))
00434 #define MEMMAP         (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x040))
00435 
00436 /* MAM defines */
00437 #define MAMCR_OFF     0
00438 #define MAMCR_PART    1
00439 #define MAMCR_FULL    2
00440 
00441 /* MEMMAP defines */
00442 #define MEMMAP_BBLK   0  /* Interrupt Vectors in Boot Block */
00443 #define MEMMAP_FLASH  1  /* Interrupt Vectors in Flash */
00444 #define MEMMAP_SRAM   2  /* Interrupt Vectors in SRAM */
00445 
00446 /* Phase Locked Loop (PLL) */
00447 #define PLLCON         (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x080))
00448 #define PLLCFG         (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x084))
00449 #define PLLSTAT        (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x088))
00450 #define PLLFEED        (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x08C))
00451 
00452 /* PLLCON Register Bit Definitions */
00453 #define PLLCON_PLLE   (1UL << 0)          /* PLL Enable */
00454 #define PLLCON_PLLC   (1UL << 1)          /* PLL Connect */
00455 
00456 /* PLLSTAT Register Bit Definitions */
00457 #define PLLSTAT_PLLE  (1UL<<24)
00458 #define PLLSTAT_PLLC  (1UL<<25)
00459 #define PLLSTAT_PLOCK (1UL<<26)
00460 
00461 
00462 /* Power Control */
00463 #define PCON           (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x0C0))
00464 #define PCONP          (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x0C4))
00465 
00466 /* Ackley: Added PCONP bit definitions */
00467                        /* bit 0 unused */
00468 #define PCTIM0         (1UL<<1)  /* Timer/counter 0 power/clock control bit */
00469 #define PCTIM1         (1UL<<2)  /* Timer/counter 1 power/clock control bit */
00470 #define PCUART0        (1UL<<3)  /* UART0 power/clock control bit */
00471 #define PCUART1        (1UL<<4)  /* UART1 power/clock control bit */
00472                        /* bit 5 unused */
00473 #define PCPWM1         (1UL<<6)  /* PWM1 power/clock control bit */
00474 #define PCI2C0         (1UL<<7)  /* I2C0 power/clock control bit */
00475 #define PCSPI          (1UL<<8)  /* SPI power/clock control bit */
00476 #define PCRTC          (1UL<<9)  /* RTC power/clock control bit */
00477 #define PCSSP1         (1UL<<10) /* SSP1 power/clock control bit */
00478 #define PCEMC          (1UL<<11) /* External Memory controller */
00479 #define PCAD           (1UL<<12) /* A/D converter power/clock control bit (needs special handling) */
00480 #define PCAN1          (1UL<<13) /* CAN Controller 1 power/clock control bit */
00481 #define PCAN2          (1UL<<14) /* CAN Controller 2 power/clock control bit */
00482                        /* bit 15 unused */
00483                        /* bit 16 unused */
00484                        /* bit 17 unused */
00485                        /* bit 18 unused */
00486 #define PCI2C1         (1UL<<19) /* I2C1 power/clock control bit */
00487                        /* bit 20 unused */
00488 #define PCSSP0         (1UL<<21) /* SSP0 power/clock control bit */
00489 #define PCTIM2         (1UL<<22) /* Timer 2 power/clock control bit */
00490 #define PCTIM3         (1UL<<23) /* Timer 3 power/clock control bit */
00491 #define PCUART2        (1UL<<24) /* UART2 power/clock control bit */
00492 #define PCUART3        (1UL<<25) /* UART3 power/clock control bit */
00493 #define PCI2C2         (1UL<<26) /* I2C2 power/clock control bit */
00494 #define PCI2S          (1UL<<27) /* I2S power/clock control bit */
00495 #define PCSDC          (1UL<<28) /* SD card power/clock control bit */
00496 #define PCGPDMA        (1UL<<29) /* GP DMA power/clock control bit */
00497 #define PCENET         (1UL<<30) /* Ethernet power/clock control bit */
00498 #define PCUSB          (1UL<<31) /* USB power/clock control bit */
00499 
00500 /* Clock Divider */
00501 /* #define APBDIV         (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x100)) */
00502 #define CCLKCFG        (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x104))
00503 #define USBCLKCFG      (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x108))
00504 #define CLKSRCSEL      (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x10C))
00505 #define PCLKSEL0       (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x1A8))
00506 #define PCLKSEL1       (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x1AC))
00507 
00508 #define CLKSRC_INT_RC    (0x00)    /* Internal RC oscillator */
00509 #define CLKSRC_MAIN_OSC  (0x01)    /* Main oscillator */
00510 #define CLKSRC_MIN_RTC   (0x02)    /* RTC oscillator */
00511 
00512 /* External Interrupts */
00513 #define EXTINT         (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x140))
00514 #define INTWAKE        (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x144))
00515 #define EXTMODE        (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x148))
00516 #define EXTPOLAR       (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x14C))
00517 
00518 /* Reset, reset source identification */
00519 #define RSIR           (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x180))
00520 
00521 /* RSID, code security protection */
00522 #define CSPR           (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x184))
00523 
00524 /* AHB configuration */
00525 #define AHBCFG1        (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x188))
00526 #define AHBCFG2        (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x18C))
00527 
00528 /* System Controls and Status */
00529 #define SCS            (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x1A0))
00530 
00531 #define SCS_GPIOM        (1UL<<0)
00532 #define SCS_EMC_RST_DIS  (1UL<<1)
00533 #define SCS_MCIPWR       (1UL<<3)
00534 #define SCS_OSCRANGE     (1UL<<4)
00535 #define SCS_OSCEN        (1UL<<5)
00536 #define SCS_OSCSTAT      (1UL<<6)
00537 
00538 
00539 /* MPMC(EMC) registers, note: all the external memory controller(EMC) registers
00540 are for LPC24xx only. */
00541 #define STATIC_MEM0_BASE                0x80000000
00542 #define STATIC_MEM1_BASE                0x81000000
00543 #define STATIC_MEM2_BASE                0x82000000
00544 #define STATIC_MEM3_BASE                0x83000000
00545 
00546 #define DYNAMIC_MEM0_BASE               0xA0000000
00547 #define DYNAMIC_MEM1_BASE               0xB0000000
00548 #define DYNAMIC_MEM2_BASE               0xC0000000
00549 #define DYNAMIC_MEM3_BASE               0xD0000000
00550 
00551 /* External Memory Controller (EMC) */
00552 #define EMC_BASE_ADDR           0xFFE08000
00553 #define EMC_CTRL       (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x000))
00554 #define EMC_STAT       (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x004))
00555 #define EMC_CONFIG     (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x008))
00556 
00557 /* Dynamic RAM access registers */
00558 #define EMC_DYN_CTRL     (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x020))
00559 #define EMC_DYN_RFSH     (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x024))
00560 #define EMC_DYN_RD_CFG   (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x028))
00561 #define EMC_DYN_RP       (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x030))
00562 #define EMC_DYN_RAS      (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x034))
00563 #define EMC_DYN_SREX     (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x038))
00564 #define EMC_DYN_APR      (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x03C))
00565 #define EMC_DYN_DAL      (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x040))
00566 #define EMC_DYN_WR       (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x044))
00567 #define EMC_DYN_RC       (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x048))
00568 #define EMC_DYN_RFC      (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x04C))
00569 #define EMC_DYN_XSR      (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x050))
00570 #define EMC_DYN_RRD      (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x054))
00571 #define EMC_DYN_MRD      (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x058))
00572 
00573 #define EMC_DYN_CFG0     (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x100))
00574 #define EMC_DYN_RASCAS0  (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x104))
00575 #define EMC_DYN_CFG1     (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x140))
00576 #define EMC_DYN_RASCAS1  (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x144))
00577 #define EMC_DYN_CFG2     (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x160))
00578 #define EMC_DYN_RASCAS2  (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x164))
00579 #define EMC_DYN_CFG3     (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x180))
00580 #define EMC_DYN_RASCAS3  (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x184))
00581 
00582 /* static RAM access registers */
00583 #define EMC_STA_CFG0      (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x200))
00584 #define EMC_STA_WAITWEN0  (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x204))
00585 #define EMC_STA_WAITOEN0  (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x208))
00586 #define EMC_STA_WAITRD0   (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x20C))
00587 #define EMC_STA_WAITPAGE0 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x210))
00588 #define EMC_STA_WAITWR0   (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x214))
00589 #define EMC_STA_WAITTURN0 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x218))
00590 
00591 #define EMC_STA_CFG1      (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x220))
00592 #define EMC_STA_WAITWEN1  (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x224))
00593 #define EMC_STA_WAITOEN1  (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x228))
00594 #define EMC_STA_WAITRD1   (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x22C))
00595 #define EMC_STA_WAITPAGE1 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x230))
00596 #define EMC_STA_WAITWR1   (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x234))
00597 #define EMC_STA_WAITTURN1 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x238))
00598 
00599 #define EMC_STA_CFG2      (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x240))
00600 #define EMC_STA_WAITWEN2  (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x244))
00601 #define EMC_STA_WAITOEN2  (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x248))
00602 #define EMC_STA_WAITRD2   (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x24C))
00603 #define EMC_STA_WAITPAGE2 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x250))
00604 #define EMC_STA_WAITWR2   (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x254))
00605 #define EMC_STA_WAITTURN2 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x258))
00606 
00607 #define EMC_STA_CFG3      (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x260))
00608 #define EMC_STA_WAITWEN3  (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x264))
00609 #define EMC_STA_WAITOEN3  (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x268))
00610 #define EMC_STA_WAITRD3   (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x26C))
00611 #define EMC_STA_WAITPAGE3 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x270))
00612 #define EMC_STA_WAITWR3   (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x274))
00613 #define EMC_STA_WAITTURN3 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x278))
00614 
00615 #define EMC_STA_EXT_WAIT  (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x880))
00616 
00617 
00618 /* Timer 0 */
00619 #define TMR0_BASE_ADDR          0xE0004000
00620 #define T0IR           (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x00))
00621 #define T0TCR          (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x04))
00622 #define T0TC           (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x08))
00623 #define T0PR           (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x0C))
00624 #define T0PC           (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x10))
00625 #define T0MCR          (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x14))
00626 #define T0MR0          (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x18))
00627 #define T0MR1          (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x1C))
00628 #define T0MR2          (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x20))
00629 #define T0MR3          (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x24))
00630 #define T0CCR          (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x28))
00631 #define T0CR0          (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x2C))
00632 #define T0CR1          (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x30))
00633 #define T0CR2          (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x34))
00634 #define T0CR3          (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x38))
00635 #define T0EMR          (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x3C))
00636 #define T0CTCR         (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x70))
00637 
00638 /* Timer 1 */
00639 #define TMR1_BASE_ADDR          0xE0008000
00640 #define T1IR           (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x00))
00641 #define T1TCR          (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x04))
00642 #define T1TC           (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x08))
00643 #define T1PR           (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x0C))
00644 #define T1PC           (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x10))
00645 #define T1MCR          (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x14))
00646 #define T1MR0          (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x18))
00647 #define T1MR1          (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x1C))
00648 #define T1MR2          (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x20))
00649 #define T1MR3          (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x24))
00650 #define T1CCR          (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x28))
00651 #define T1CR0          (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x2C))
00652 #define T1CR1          (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x30))
00653 #define T1CR2          (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x34))
00654 #define T1CR3          (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x38))
00655 #define T1EMR          (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x3C))
00656 #define T1CTCR         (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x70))
00657 
00658 /* Timer 2 */
00659 #define TMR2_BASE_ADDR          0xE0070000
00660 #define T2IR           (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x00))
00661 #define T2TCR          (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x04))
00662 #define T2TC           (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x08))
00663 #define T2PR           (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x0C))
00664 #define T2PC           (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x10))
00665 #define T2MCR          (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x14))
00666 #define T2MR0          (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x18))
00667 #define T2MR1          (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x1C))
00668 #define T2MR2          (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x20))
00669 #define T2MR3          (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x24))
00670 #define T2CCR          (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x28))
00671 #define T2CR0          (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x2C))
00672 #define T2CR1          (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x30))
00673 #define T2CR2          (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x34))
00674 #define T2CR3          (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x38))
00675 #define T2EMR          (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x3C))
00676 #define T2CTCR         (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x70))
00677 
00678 /* Timer 3 */
00679 #define TMR3_BASE_ADDR          0xE0074000
00680 #define T3IR           (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x00))
00681 #define T3TCR          (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x04))
00682 #define T3TC           (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x08))
00683 #define T3PR           (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x0C))
00684 #define T3PC           (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x10))
00685 #define T3MCR          (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x14))
00686 #define T3MR0          (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x18))
00687 #define T3MR1          (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x1C))
00688 #define T3MR2          (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x20))
00689 #define T3MR3          (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x24))
00690 #define T3CCR          (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x28))
00691 #define T3CR0          (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x2C))
00692 #define T3CR1          (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x30))
00693 #define T3CR2          (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x34))
00694 #define T3CR3          (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x38))
00695 #define T3EMR          (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x3C))
00696 #define T3CTCR         (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x70))
00697 
00698 /* Ackley: Added Generic Timer offsets */
00699 #define TxIR    0x00
00700 #define TxTCR   0x04
00701 #define TxTC    0x08
00702 #define TxPR    0x0C
00703 #define TxPC    0x10
00704 #define TxMCR   0x14
00705 #define TxMR0   0x18
00706 #define TxMR1   0x1C
00707 #define TxMR2   0x20
00708 #define TxMR3   0x24
00709 #define TxCCR   0x28
00710 #define TxCR0   0x2C
00711 #define TxCR1   0x30
00712 #define TxCR2   0x34
00713 #define TxCR3   0x38
00714 #define TxEMR   0x3C
00715 #define TxCTCR  0x70
00716 
00717 /* Pulse Width Modulator (PWM) */
00718 #define PWM0_BASE_ADDR          0xE0014000
00719 #define PWM0IR          (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x00))
00720 #define PWM0TCR         (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x04))
00721 #define PWM0TC          (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x08))
00722 #define PWM0PR          (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x0C))
00723 #define PWM0PC          (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x10))
00724 #define PWM0MCR         (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x14))
00725 #define PWM0MR0         (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x18))
00726 #define PWM0MR1         (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x1C))
00727 #define PWM0MR2         (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x20))
00728 #define PWM0MR3         (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x24))
00729 #define PWM0CCR         (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x28))
00730 #define PWM0CR0         (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x2C))
00731 #define PWM0CR1         (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x30))
00732 #define PWM0CR2         (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x34))
00733 #define PWM0CR3         (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x38))
00734 #define PWM0EMR         (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x3C))
00735 #define PWM0MR4         (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x40))
00736 #define PWM0MR5         (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x44))
00737 #define PWM0MR6         (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x48))
00738 #define PWM0PCR         (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x4C))
00739 #define PWM0LER         (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x50))
00740 #define PWM0CTCR        (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x70))
00741 
00742 #define PWM1_BASE_ADDR          0xE0018000
00743 #define PWM1IR          (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x00))
00744 #define PWM1TCR         (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x04))
00745 #define PWM1TC          (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x08))
00746 #define PWM1PR          (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x0C))
00747 #define PWM1PC          (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x10))
00748 #define PWM1MCR         (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x14))
00749 #define PWM1MR0         (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x18))
00750 #define PWM1MR1         (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x1C))
00751 #define PWM1MR2         (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x20))
00752 #define PWM1MR3         (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x24))
00753 #define PWM1CCR         (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x28))
00754 #define PWM1CR0         (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x2C))
00755 #define PWM1CR1         (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x30))
00756 #define PWM1CR2         (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x34))
00757 #define PWM1CR3         (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x38))
00758 #define PWM1EMR         (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x3C))
00759 #define PWM1MR4         (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x40))
00760 #define PWM1MR5         (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x44))
00761 #define PWM1MR6         (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x48))
00762 #define PWM1PCR         (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x4C))
00763 #define PWM1LER         (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x50))
00764 #define PWM1CTCR        (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x70))
00765 
00766 /* Ackley: Added Generic UART offsets */
00767 #define UxRBR          0x00
00768 #define UxTHR          0x00
00769 #define UxDLL          0x00
00770 #define UxDLM          0x04
00771 #define UxIER          0x04
00772 #define UxIIR          0x08
00773 #define UxFCR          0x08
00774 #define UxLCR          0x0C
00775 #define UxLSR          0x14
00776 #define UxSCR          0x1C
00777 #define UxACR          0x20
00778 #define UxICR          0x24
00779 #define UxFDR          0x28
00780 #define UxTER          0x30
00781 
00782 /* Universal Asynchronous Receiver Transmitter 0 (UART0) */
00783 #define UART0_BASE_ADDR         0xE000C000
00784 #define U0RBR          (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x00))
00785 #define U0THR          (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x00))
00786 #define U0DLL          (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x00))
00787 #define U0DLM          (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x04))
00788 #define U0IER          (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x04))
00789 #define U0IIR          (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x08))
00790 #define U0FCR          (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x08))
00791 #define U0LCR          (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x0C))
00792 #define U0LSR          (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x14))
00793 #define U0SCR          (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x1C))
00794 #define U0ACR          (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x20))
00795 #define U0ICR          (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x24))
00796 #define U0FDR          (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x28))
00797 #define U0TER          (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x30))
00798 
00799 /* Universal Asynchronous Receiver Transmitter 1 (UART1) */
00800 #define UART1_BASE_ADDR         0xE0010000
00801 #define U1RBR          (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x00))
00802 #define U1THR          (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x00))
00803 #define U1DLL          (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x00))
00804 #define U1DLM          (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x04))
00805 #define U1IER          (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x04))
00806 #define U1IIR          (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x08))
00807 #define U1FCR          (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x08))
00808 #define U1LCR          (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x0C))
00809 #define U1MCR          (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x10))
00810 #define U1LSR          (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x14))
00811 #define U1MSR          (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x18))
00812 #define U1SCR          (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x1C))
00813 #define U1ACR          (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x20))
00814 /*#define U1ICR          (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x24)) ACKLEY -- Only this one was missing from the file, why? */
00815 #define U1FDR          (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x28))
00816 #define U1TER          (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x30))
00817 
00818 /* Universal Asynchronous Receiver Transmitter 2 (UART2) */
00819 #define UART2_BASE_ADDR         0xE0078000
00820 #define U2RBR          (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x00))
00821 #define U2THR          (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x00))
00822 #define U2DLL          (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x00))
00823 #define U2DLM          (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x04))
00824 #define U2IER          (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x04))
00825 #define U2IIR          (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x08))
00826 #define U2FCR          (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x08))
00827 #define U2LCR          (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x0C))
00828 #define U2LSR          (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x14))
00829 #define U2SCR          (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x1C))
00830 #define U2ACR          (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x20))
00831 #define U2ICR          (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x24))
00832 #define U2FDR          (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x28))
00833 #define U2TER          (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x30))
00834 
00835 /* Universal Asynchronous Receiver Transmitter 3 (UART3) */
00836 #define UART3_BASE_ADDR         0xE007C000
00837 #define U3RBR          (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x00))
00838 #define U3THR          (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x00))
00839 #define U3DLL          (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x00))
00840 #define U3DLM          (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x04))
00841 #define U3IER          (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x04))
00842 #define U3IIR          (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x08))
00843 #define U3FCR          (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x08))
00844 #define U3LCR          (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x0C))
00845 #define U3LSR          (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x14))
00846 #define U3SCR          (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x1C))
00847 #define U3ACR          (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x20))
00848 #define U3ICR          (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x24))
00849 #define U3FDR          (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x28))
00850 #define U3TER          (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x30))
00851 
00852 /* I2C Interface 0 */
00853 #define I2C0_BASE_ADDR          0xE001C000
00854 #define I20CONSET      (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x00))
00855 #define I20STAT        (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x04))
00856 #define I20DAT         (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x08))
00857 #define I20ADR         (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x0C))
00858 #define I20SCLH        (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x10))
00859 #define I20SCLL        (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x14))
00860 #define I20CONCLR      (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x18))
00861 
00862 /* I2C Interface 1 */
00863 #define I2C1_BASE_ADDR          0xE005C000
00864 #define I21CONSET      (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x00))
00865 #define I21STAT        (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x04))
00866 #define I21DAT         (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x08))
00867 #define I21ADR         (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x0C))
00868 #define I21SCLH        (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x10))
00869 #define I21SCLL        (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x14))
00870 #define I21CONCLR      (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x18))
00871 
00872 /* I2C Interface 2 */
00873 #define I2C2_BASE_ADDR          0xE0080000
00874 #define I22CONSET      (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x00))
00875 #define I22STAT        (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x04))
00876 #define I22DAT         (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x08))
00877 #define I22ADR         (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x0C))
00878 #define I22SCLH        (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x10))
00879 #define I22SCLL        (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x14))
00880 #define I22CONCLR      (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x18))
00881 
00882 /* SPI0 (Serial Peripheral Interface 0) */
00883 #define SPI0_BASE_ADDR          0xE0020000
00884 #define S0SPCR         (*(volatile unsigned long *)(SPI0_BASE_ADDR + 0x00))
00885 #define S0SPSR         (*(volatile unsigned long *)(SPI0_BASE_ADDR + 0x04))
00886 #define S0SPDR         (*(volatile unsigned long *)(SPI0_BASE_ADDR + 0x08))
00887 #define S0SPCCR        (*(volatile unsigned long *)(SPI0_BASE_ADDR + 0x0C))
00888 #define S0SPINT        (*(volatile unsigned long *)(SPI0_BASE_ADDR + 0x1C))
00889 
00890 /* SSP0 Controller */
00891 #define SSP0_BASE_ADDR          0xE0068000
00892 #define SSP0CR0        (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x00))
00893 #define SSP0CR1        (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x04))
00894 #define SSP0DR         (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x08))
00895 #define SSP0SR         (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x0C))
00896 #define SSP0CPSR       (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x10))
00897 #define SSP0IMSC       (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x14))
00898 #define SSP0RIS        (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x18))
00899 #define SSP0MIS        (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x1C))
00900 #define SSP0ICR        (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x20))
00901 #define SSP0DMACR      (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x24))
00902 
00903 /* SSP1 Controller */
00904 #define SSP1_BASE_ADDR          0xE0030000
00905 #define SSP1CR0        (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x00))
00906 #define SSP1CR1        (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x04))
00907 #define SSP1DR         (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x08))
00908 #define SSP1SR         (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x0C))
00909 #define SSP1CPSR       (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x10))
00910 #define SSP1IMSC       (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x14))
00911 #define SSP1RIS        (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x18))
00912 #define SSP1MIS        (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x1C))
00913 #define SSP1ICR        (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x20))
00914 #define SSP1DMACR      (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x24))
00915 
00916 
00917 /* Real Time Clock */
00918 #define RTC_BASE_ADDR           0xE0024000
00919 #define RTC_ILR         (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x00))
00920 #define RTC_CTC         (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x04))
00921 #define RTC_CCR         (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x08))
00922 #define RTC_CIIR        (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x0C))
00923 #define RTC_AMR         (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x10))
00924 #define RTC_CTIME0      (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x14))
00925 #define RTC_CTIME1      (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x18))
00926 #define RTC_CTIME2      (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x1C))
00927 #define RTC_SEC         (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x20))
00928 #define RTC_MIN         (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x24))
00929 #define RTC_HOUR        (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x28))
00930 #define RTC_DOM         (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x2C))
00931 #define RTC_DOW         (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x30))
00932 #define RTC_DOY         (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x34))
00933 #define RTC_MONTH       (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x38))
00934 #define RTC_YEAR        (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x3C))
00935 #define RTC_CISS        (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x40))
00936 #define RTC_ALSEC       (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x60))
00937 #define RTC_ALMIN       (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x64))
00938 #define RTC_ALHOUR      (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x68))
00939 #define RTC_ALDOM       (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x6C))
00940 #define RTC_ALDOW       (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x70))
00941 #define RTC_ALDOY       (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x74))
00942 #define RTC_ALMON       (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x78))
00943 #define RTC_ALYEAR      (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x7C))
00944 #define RTC_PREINT      (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x80))
00945 #define RTC_PREFRAC     (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x84))
00946 
00947 
00948 /* A/D Converter 0 (AD0) */
00949 #define AD0_BASE_ADDR           0xE0034000
00950 #define AD0CR          (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x00))
00951 #define AD0GDR         (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x04))
00952 #define AD0INTEN       (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x0C))
00953 #define AD0DR0         (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x10))
00954 #define AD0DR1         (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x14))
00955 #define AD0DR2         (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x18))
00956 #define AD0DR3         (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x1C))
00957 #define AD0DR4         (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x20))
00958 #define AD0DR5         (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x24))
00959 #define AD0DR6         (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x28))
00960 #define AD0DR7         (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x2C))
00961 #define AD0STAT        (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x30))
00962 
00963 
00964 /* D/A Converter */
00965 #define DAC_BASE_ADDR           0xE006C000
00966 #define DACR           (*(volatile unsigned long *)(DAC_BASE_ADDR + 0x00))
00967 
00968 
00969 /* Watchdog */
00970 #define WDG_BASE_ADDR           0xE0000000
00971 #define WDMOD          (*(volatile unsigned long *)(WDG_BASE_ADDR + 0x00))
00972 #define WDTC           (*(volatile unsigned long *)(WDG_BASE_ADDR + 0x04))
00973 #define WDFEED         (*(volatile unsigned long *)(WDG_BASE_ADDR + 0x08))
00974 #define WDTV           (*(volatile unsigned long *)(WDG_BASE_ADDR + 0x0C))
00975 #define WDCLKSEL       (*(volatile unsigned long *)(WDG_BASE_ADDR + 0x10))
00976 
00977 /* CAN CONTROLLERS AND ACCEPTANCE FILTER */
00978 #define CAN_ACCEPT_BASE_ADDR            0xE003C000
00979 #define CAN_AFMR                (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x00))
00980 #define CAN_SFF_SA              (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x04))
00981 #define CAN_SFF_GRP_SA  (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x08))
00982 #define CAN_EFF_SA              (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x0C))
00983 #define CAN_EFF_GRP_SA  (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x10))
00984 #define CAN_EOT                 (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x14))
00985 #define CAN_LUT_ERR_ADR (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x18))
00986 #define CAN_LUT_ERR     (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x1C))
00987 
00988 #define CAN_CENTRAL_BASE_ADDR           0xE0040000
00989 #define CAN_TX_SR       (*(volatile unsigned long *)(CAN_CENTRAL_BASE_ADDR + 0x00))
00990 #define CAN_RX_SR       (*(volatile unsigned long *)(CAN_CENTRAL_BASE_ADDR + 0x04))
00991 #define CAN_MSR         (*(volatile unsigned long *)(CAN_CENTRAL_BASE_ADDR + 0x08))
00992 
00993 #define CAN1_BASE_ADDR          0xE0044000
00994 #define CAN1MOD         (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x00))
00995 #define CAN1CMR         (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x04))
00996 #define CAN1GSR         (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x08))
00997 #define CAN1ICR         (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x0C))
00998 #define CAN1IER         (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x10))
00999 #define CAN1BTR         (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x14))
01000 #define CAN1EWL         (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x18))
01001 #define CAN1SR          (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x1C))
01002 #define CAN1RFS         (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x20))
01003 #define CAN1RID         (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x24))
01004 #define CAN1RDA         (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x28))
01005 #define CAN1RDB         (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x2C))
01006 
01007 #define CAN1TFI1        (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x30))
01008 #define CAN1TID1        (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x34))
01009 #define CAN1TDA1        (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x38))
01010 #define CAN1TDB1        (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x3C))
01011 #define CAN1TFI2        (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x40))
01012 #define CAN1TID2        (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x44))
01013 #define CAN1TDA2        (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x48))
01014 #define CAN1TDB2        (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x4C))
01015 #define CAN1TFI3        (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x50))
01016 #define CAN1TID3        (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x54))
01017 #define CAN1TDA3        (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x58))
01018 #define CAN1TDB3        (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x5C))
01019 
01020 #define CAN2_BASE_ADDR          0xE0048000
01021 #define CAN2MOD         (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x00))
01022 #define CAN2CMR         (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x04))
01023 #define CAN2GSR         (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x08))
01024 #define CAN2ICR         (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x0C))
01025 #define CAN2IER         (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x10))
01026 #define CAN2BTR         (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x14))
01027 #define CAN2EWL         (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x18))
01028 #define CAN2SR          (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x1C))
01029 #define CAN2RFS         (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x20))
01030 #define CAN2RID         (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x24))
01031 #define CAN2RDA         (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x28))
01032 #define CAN2RDB         (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x2C))
01033 
01034 #define CAN2TFI1        (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x30))
01035 #define CAN2TID1        (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x34))
01036 #define CAN2TDA1        (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x38))
01037 #define CAN2TDB1        (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x3C))
01038 #define CAN2TFI2        (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x40))
01039 #define CAN2TID2        (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x44))
01040 #define CAN2TDA2        (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x48))
01041 #define CAN2TDB2        (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x4C))
01042 #define CAN2TFI3        (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x50))
01043 #define CAN2TID3        (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x54))
01044 #define CAN2TDA3        (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x58))
01045 #define CAN2TDB3        (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x5C))
01046 
01047 
01048 /* MultiMedia Card Interface(MCI) Controller */
01049 #define MCI_BASE_ADDR           0xE008C000
01050 #define MCI_POWER      (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x00))
01051 #define MCI_CLOCK      (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x04))
01052 #define MCI_ARGUMENT   (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x08))
01053 #define MCI_COMMAND    (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x0C))
01054 #define MCI_RESP_CMD   (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x10))
01055 #define MCI_RESP0      (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x14))
01056 #define MCI_RESP1      (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x18))
01057 #define MCI_RESP2      (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x1C))
01058 #define MCI_RESP3      (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x20))
01059 #define MCI_DATA_TMR   (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x24))
01060 #define MCI_DATA_LEN   (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x28))
01061 #define MCI_DATA_CTRL  (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x2C))
01062 #define MCI_DATA_CNT   (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x30))
01063 #define MCI_STATUS     (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x34))
01064 #define MCI_CLEAR      (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x38))
01065 #define MCI_MASK0      (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x3C))
01066 #define MCI_MASK1      (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x40))
01067 #define MCI_FIFO_CNT   (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x48))
01068 #define MCI_FIFO       (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x80))
01069 
01070 
01071 /* I2S Interface Controller (I2S) */
01072 #define I2S_BASE_ADDR           0xE0088000
01073 #define I2S_DAO        (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x00))
01074 #define I2S_DAI        (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x04))
01075 #define I2S_TX_FIFO    (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x08))
01076 #define I2S_RX_FIFO    (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x0C))
01077 #define I2S_STATE      (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x10))
01078 #define I2S_DMA1       (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x14))
01079 #define I2S_DMA2       (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x18))
01080 #define I2S_IRQ        (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x1C))
01081 #define I2S_TXRATE     (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x20))
01082 #define I2S_RXRATE     (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x24))
01083 
01084 
01085 /* General-purpose DMA Controller */
01086 #define DMA_BASE_ADDR           0xFFE04000
01087 #define GPDMA_INT_STAT         (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x000))
01088 #define GPDMA_INT_TCSTAT       (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x004))
01089 #define GPDMA_INT_TCCLR        (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x008))
01090 #define GPDMA_INT_ERR_STAT     (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x00C))
01091 #define GPDMA_INT_ERR_CLR      (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x010))
01092 #define GPDMA_RAW_INT_TCSTAT   (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x014))
01093 #define GPDMA_RAW_INT_ERR_STAT (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x018))
01094 #define GPDMA_ENABLED_CHNS     (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x01C))
01095 #define GPDMA_SOFT_BREQ        (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x020))
01096 #define GPDMA_SOFT_SREQ        (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x024))
01097 #define GPDMA_SOFT_LBREQ       (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x028))
01098 #define GPDMA_SOFT_LSREQ       (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x02C))
01099 #define GPDMA_CONFIG           (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x030))
01100 #define GPDMA_SYNC             (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x034))
01101 
01102 /* DMA channel 0 registers */
01103 #define GPDMA_CH0_SRC      (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x100))
01104 #define GPDMA_CH0_DEST     (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x104))
01105 #define GPDMA_CH0_LLI      (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x108))
01106 #define GPDMA_CH0_CTRL     (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x10C))
01107 #define GPDMA_CH0_CFG      (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x110))
01108 
01109 /* DMA channel 1 registers */
01110 #define GPDMA_CH1_SRC      (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x120))
01111 #define GPDMA_CH1_DEST     (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x124))
01112 #define GPDMA_CH1_LLI      (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x128))
01113 #define GPDMA_CH1_CTRL     (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x12C))
01114 #define GPDMA_CH1_CFG      (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x130))
01115 
01116 
01117 /* USB Controller */
01118 #define USB_INT_BASE_ADDR       0xE01FC1C0
01119 #define USB_BASE_ADDR           0xFFE0C200              /* USB Base Address */
01120 
01121 #define USB_INT_STAT    (*(volatile unsigned long *)(USB_INT_BASE_ADDR + 0x00))
01122 
01123 /* USB Device Interrupt Registers */
01124 #define DEV_INT_STAT    (*(volatile unsigned long *)(USB_BASE_ADDR + 0x00))
01125 #define DEV_INT_EN      (*(volatile unsigned long *)(USB_BASE_ADDR + 0x04))
01126 #define DEV_INT_CLR     (*(volatile unsigned long *)(USB_BASE_ADDR + 0x08))
01127 #define DEV_INT_SET     (*(volatile unsigned long *)(USB_BASE_ADDR + 0x0C))
01128 #define DEV_INT_PRIO    (*(volatile unsigned long *)(USB_BASE_ADDR + 0x2C))
01129 
01130 /* USB Device Endpoint Interrupt Registers */
01131 #define EP_INT_STAT     (*(volatile unsigned long *)(USB_BASE_ADDR + 0x30))
01132 #define EP_INT_EN       (*(volatile unsigned long *)(USB_BASE_ADDR + 0x34))
01133 #define EP_INT_CLR      (*(volatile unsigned long *)(USB_BASE_ADDR + 0x38))
01134 #define EP_INT_SET      (*(volatile unsigned long *)(USB_BASE_ADDR + 0x3C))
01135 #define EP_INT_PRIO     (*(volatile unsigned long *)(USB_BASE_ADDR + 0x40))
01136 
01137 /* USB Device Endpoint Realization Registers */
01138 #define REALIZE_EP      (*(volatile unsigned long *)(USB_BASE_ADDR + 0x44))
01139 #define EP_INDEX        (*(volatile unsigned long *)(USB_BASE_ADDR + 0x48))
01140 #define MAXPACKET_SIZE  (*(volatile unsigned long *)(USB_BASE_ADDR + 0x4C))
01141 
01142 /* USB Device Command Reagisters */
01143 #define CMD_CODE        (*(volatile unsigned long *)(USB_BASE_ADDR + 0x10))
01144 #define CMD_DATA        (*(volatile unsigned long *)(USB_BASE_ADDR + 0x14))
01145 
01146 /* USB Device Data Transfer Registers */
01147 #define RX_DATA         (*(volatile unsigned long *)(USB_BASE_ADDR + 0x18))
01148 #define TX_DATA         (*(volatile unsigned long *)(USB_BASE_ADDR + 0x1C))
01149 #define RX_PLENGTH      (*(volatile unsigned long *)(USB_BASE_ADDR + 0x20))
01150 #define TX_PLENGTH      (*(volatile unsigned long *)(USB_BASE_ADDR + 0x24))
01151 #define USB_CTRL        (*(volatile unsigned long *)(USB_BASE_ADDR + 0x28))
01152 
01153 /* USB Device DMA Registers */
01154 #define DMA_REQ_STAT        (*(volatile unsigned long *)(USB_BASE_ADDR + 0x50))
01155 #define DMA_REQ_CLR         (*(volatile unsigned long *)(USB_BASE_ADDR + 0x54))
01156 #define DMA_REQ_SET         (*(volatile unsigned long *)(USB_BASE_ADDR + 0x58))
01157 #define UDCA_HEAD           (*(volatile unsigned long *)(USB_BASE_ADDR + 0x80))
01158 #define EP_DMA_STAT         (*(volatile unsigned long *)(USB_BASE_ADDR + 0x84))
01159 #define EP_DMA_EN           (*(volatile unsigned long *)(USB_BASE_ADDR + 0x88))
01160 #define EP_DMA_DIS          (*(volatile unsigned long *)(USB_BASE_ADDR + 0x8C))
01161 #define DMA_INT_STAT        (*(volatile unsigned long *)(USB_BASE_ADDR + 0x90))
01162 #define DMA_INT_EN          (*(volatile unsigned long *)(USB_BASE_ADDR + 0x94))
01163 #define EOT_INT_STAT        (*(volatile unsigned long *)(USB_BASE_ADDR + 0xA0))
01164 #define EOT_INT_CLR         (*(volatile unsigned long *)(USB_BASE_ADDR + 0xA4))
01165 #define EOT_INT_SET         (*(volatile unsigned long *)(USB_BASE_ADDR + 0xA8))
01166 #define NDD_REQ_INT_STAT    (*(volatile unsigned long *)(USB_BASE_ADDR + 0xAC))
01167 #define NDD_REQ_INT_CLR     (*(volatile unsigned long *)(USB_BASE_ADDR + 0xB0))
01168 #define NDD_REQ_INT_SET     (*(volatile unsigned long *)(USB_BASE_ADDR + 0xB4))
01169 #define SYS_ERR_INT_STAT    (*(volatile unsigned long *)(USB_BASE_ADDR + 0xB8))
01170 #define SYS_ERR_INT_CLR     (*(volatile unsigned long *)(USB_BASE_ADDR + 0xBC))
01171 #define SYS_ERR_INT_SET     (*(volatile unsigned long *)(USB_BASE_ADDR + 0xC0))
01172 
01173 /* USB Host and OTG registers are for LPC24xx only */
01174 /* USB Host Controller */
01175 #define USBHC_BASE_ADDR         0xFFE0C000
01176 #define HC_REVISION         (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x00))
01177 #define HC_CONTROL          (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x04))
01178 #define HC_CMD_STAT         (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x08))
01179 #define HC_INT_STAT         (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x0C))
01180 #define HC_INT_EN           (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x10))
01181 #define HC_INT_DIS          (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x14))
01182 #define HC_HCCA             (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x18))
01183 #define HC_PERIOD_CUR_ED    (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x1C))
01184 #define HC_CTRL_HEAD_ED     (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x20))
01185 #define HC_CTRL_CUR_ED      (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x24))
01186 #define HC_BULK_HEAD_ED     (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x28))
01187 #define HC_BULK_CUR_ED      (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x2C))
01188 #define HC_DONE_HEAD        (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x30))
01189 #define HC_FM_INTERVAL      (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x34))
01190 #define HC_FM_REMAINING     (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x38))
01191 #define HC_FM_NUMBER        (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x3C))
01192 #define HC_PERIOD_START     (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x40))
01193 #define HC_LS_THRHLD        (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x44))
01194 #define HC_RH_DESCA         (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x48))
01195 #define HC_RH_DESCB         (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x4C))
01196 #define HC_RH_STAT          (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x50))
01197 #define HC_RH_PORT_STAT1    (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x54))
01198 #define HC_RH_PORT_STAT2    (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x58))
01199 
01200 /* USB OTG Controller */
01201 #define USBOTG_BASE_ADDR        0xFFE0C100
01202 #define OTG_INT_STAT        (*(volatile unsigned long *)(USBOTG_BASE_ADDR + 0x00))
01203 #define OTG_INT_EN          (*(volatile unsigned long *)(USBOTG_BASE_ADDR + 0x04))
01204 #define OTG_INT_SET         (*(volatile unsigned long *)(USBOTG_BASE_ADDR + 0x08))
01205 #define OTG_INT_CLR         (*(volatile unsigned long *)(USBOTG_BASE_ADDR + 0x0C))
01206 /* On LPC23xx, the name is USBPortSel, on LPC24xx, the name is OTG_STAT_CTRL */
01207 #define OTG_STAT_CTRL       (*(volatile unsigned long *)(USBOTG_BASE_ADDR + 0x10))
01208 #define OTG_TIMER           (*(volatile unsigned long *)(USBOTG_BASE_ADDR + 0x14))
01209 
01210 #define USBOTG_I2C_BASE_ADDR    0xFFE0C300
01211 #define OTG_I2C_RX          (*(volatile unsigned long *)(USBOTG_I2C_BASE_ADDR + 0x00))
01212 #define OTG_I2C_TX          (*(volatile unsigned long *)(USBOTG_I2C_BASE_ADDR + 0x00))
01213 #define OTG_I2C_STS         (*(volatile unsigned long *)(USBOTG_I2C_BASE_ADDR + 0x04))
01214 #define OTG_I2C_CTL         (*(volatile unsigned long *)(USBOTG_I2C_BASE_ADDR + 0x08))
01215 #define OTG_I2C_CLKHI       (*(volatile unsigned long *)(USBOTG_I2C_BASE_ADDR + 0x0C))
01216 #define OTG_I2C_CLKLO       (*(volatile unsigned long *)(USBOTG_I2C_BASE_ADDR + 0x10))
01217 
01218 /* On LPC23xx, the names are USBClkCtrl and USBClkSt; on LPC24xx, the names are
01219 OTG_CLK_CTRL and OTG_CLK_STAT respectively. */
01220 #define USBOTG_CLK_BASE_ADDR    0xFFE0CFF0
01221 #define OTG_CLK_CTRL        (*(volatile unsigned long *)(USBOTG_CLK_BASE_ADDR + 0x04))
01222 #define OTG_CLK_STAT        (*(volatile unsigned long *)(USBOTG_CLK_BASE_ADDR + 0x08))
01223 
01224 /* Note: below three register name convention is for LPC23xx USB device only, match
01225 with the spec. update in USB Device Section. */
01226 #define USBPortSel          (*(volatile unsigned long *)(USBOTG_BASE_ADDR + 0x10))
01227 #define USBClkCtrl          (*(volatile unsigned long *)(USBOTG_CLK_BASE_ADDR + 0x04))
01228 #define USBClkSt            (*(volatile unsigned long *)(USBOTG_CLK_BASE_ADDR + 0x08))
01229 
01230 /* Ethernet MAC (32 bit data bus) -- all registers are RW unless indicated in parentheses */
01231 #define MAC_BASE_ADDR           0xFFE00000 /* AHB Peripheral # 0 */
01232 #define MAC_MAC1            (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x000)) /* MAC config reg 1 */
01233 #define MAC_MAC2            (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x004)) /* MAC config reg 2 */
01234 #define MAC_IPGT            (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x008)) /* b2b InterPacketGap reg */
01235 #define MAC_IPGR            (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x00C)) /* non b2b InterPacketGap reg */
01236 #define MAC_CLRT            (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x010)) /* CoLlision window/ReTry reg */
01237 #define MAC_MAXF            (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x014)) /* MAXimum Frame reg */
01238 #define MAC_SUPP            (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x018)) /* PHY SUPPort reg */
01239 #define MAC_TEST            (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x01C)) /* TEST reg */
01240 #define MAC_MCFG            (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x020)) /* MII Mgmt ConFiG reg */
01241 #define MAC_MCMD            (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x024)) /* MII Mgmt CoMmanD reg */
01242 #define MAC_MADR            (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x028)) /* MII Mgmt ADdRess reg */
01243 #define MAC_MWTD            (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x02C)) /* MII Mgmt WriTe Data reg (WO) */
01244 #define MAC_MRDD            (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x030)) /* MII Mgmt ReaD Data reg (RO) */
01245 #define MAC_MIND            (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x034)) /* MII Mgmt INDicators reg (RO) */
01246 
01247 #define MAC_SA0             (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x040)) /* Station Address 0 reg */
01248 #define MAC_SA1             (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x044)) /* Station Address 1 reg */
01249 #define MAC_SA2             (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x048)) /* Station Address 2 reg */
01250 
01251 #define MAC_COMMAND         (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x100)) /* Command reg */
01252 #define MAC_STATUS          (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x104)) /* Status reg (RO) */
01253 #define MAC_RXDESCRIPTOR    (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x108)) /* Rx descriptor base address reg */
01254 #define MAC_RXSTATUS        (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x10C)) /* Rx status base address reg */
01255 #define MAC_RXDESCRIPTORNUM (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x110)) /* Rx number of descriptors reg */
01256 #define MAC_RXPRODUCEINDEX  (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x114)) /* Rx produce index reg (RO) */
01257 #define MAC_RXCONSUMEINDEX  (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x118)) /* Rx consume index reg */
01258 #define MAC_TXDESCRIPTOR    (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x11C)) /* Tx descriptor base address reg */
01259 #define MAC_TXSTATUS        (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x120)) /* Tx status base address reg */
01260 #define MAC_TXDESCRIPTORNUM (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x124)) /* Tx number of descriptors reg */
01261 #define MAC_TXPRODUCEINDEX  (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x128)) /* Tx produce index reg */
01262 #define MAC_TXCONSUMEINDEX  (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x12C)) /* Tx consume index reg (RO) */
01263 
01264 #define MAC_TSV0            (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x158)) /* Tx status vector 0 reg (RO) */
01265 #define MAC_TSV1            (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x15C)) /* Tx status vector 1 reg (RO) */
01266 #define MAC_RSV             (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x160)) /* Rx status vector reg (RO) */
01267 
01268 #define MAC_FLOWCONTROLCNT  (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x170)) /* Flow control counter reg */
01269 #define MAC_FLOWCONTROLSTS  (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x174)) /* Flow control status reg */
01270 
01271 #define MAC_RXFILTERCTRL    (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x200)) /* Rx filter ctrl reg */
01272 #define MAC_RXFILTERWOLSTS  (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x204)) /* Rx filter WoL status reg (RO) */
01273 #define MAC_RXFILTERWOLCLR  (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x208)) /* Rx filter WoL clear reg (WO) */
01274 
01275 #define MAC_HASHFILTERL     (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x210)) /* Hash filter LSBs reg */
01276 #define MAC_HASHFILTERH     (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x214)) /* Hash filter MSBs reg */
01277 
01278 #define MAC_INTSTATUS       (*(volatile unsigned long *)(MAC_BASE_ADDR + 0xFE0)) /* Interrupt status reg (RO) */
01279 #define MAC_INTENABLE       (*(volatile unsigned long *)(MAC_BASE_ADDR + 0xFE4)) /* Interrupt enable reg  */
01280 #define MAC_INTCLEAR        (*(volatile unsigned long *)(MAC_BASE_ADDR + 0xFE8)) /* Interrupt clear reg (WO) */
01281 #define MAC_INTSET          (*(volatile unsigned long *)(MAC_BASE_ADDR + 0xFEC)) /* Interrupt set reg (WO) */
01282 
01283 #define MAC_POWERDOWN       (*(volatile unsigned long *)(MAC_BASE_ADDR + 0xFF4)) /* Power-down reg */
01284 #define MAC_MODULEID        (*(volatile unsigned long *)(MAC_BASE_ADDR + 0xFFC)) /* Module ID reg (RO) */
01285 
01286 
01287 /* Some bit-mask definitions - mthomas */
01288 
01289 /* Timers */
01290 #define TxIR_MR0_Interrupt (1UL<<0)
01291 #define TxIR_MR1_Interrupt (1UL<<1)
01292 #define TxIR_MR2_Interrupt (1UL<<2)
01293 #define TxIR_MR3_Interrupt (1UL<<3)
01294 #define TxIR_CR0_Interrupt (1UL<<4)
01295 #define TxIR_CR1_Interrupt (1UL<<5)
01296 #define TxIR_CR2_Interrupt (1UL<<6)
01297 #define TxIR_CR3_Interrupt (1UL<<7)
01298 
01299 #define TxTCR_Counter_Enable (1UL<<0)
01300 #define TxTCR_Counter_Reset  (1UL<<1)
01301 
01302 #define TxMCR_MR0I  (1UL<<0)
01303 #define TxMCR_MR0R  (1UL<<1)
01304 #define TxMCR_MR0S  (1UL<<2)
01305 #define TxMCR_MR1I  (1UL<<3)
01306 #define TxMCR_MR1R  (1UL<<4)
01307 #define TxMCR_MR1S  (1UL<<5)
01308 #define TxMCR_MR2I  (1UL<<6)
01309 #define TxMCR_MR2R  (1UL<<7)
01310 #define TxMCR_MR2S  (1UL<<8)
01311 #define TxMCR_MR3I  (1UL<<9)
01312 #define TxMCR_MR3R  (1UL<<10)
01313 #define TxMCR_MR3S  (1UL<<11)
01314 
01315 /* VIC */
01316 #define VIC_CHAN_NUM_WDT      0
01317 #define VIC_CHAN_NUM_UNUSED   1
01318 #define VIC_CHAN_NUM_ARM_Core_DgbCommRX 2
01319 #define VIC_CHAN_NUM_ARM_Core_DbgCommTX 3
01320 #define VIC_CHAN_NUM_Timer0   4
01321 #define VIC_CHAN_NUM_Timer1   5
01322 #define VIC_CHAN_NUM_UART0    6
01323 #define VIC_CHAN_NUM_UART1    7
01324 #define VIC_CHAN_NUM_PWM1     8
01325 #define VIC_CHAN_NUM_I2C0     9
01326 #define VIC_CHAN_NUM_SPI     10
01327 #define VIC_CHAN_NUM_SSP0    10
01328 #define VIC_CHAN_NUM_SSP1    11
01329 #define VIC_CHAN_NUM_PLL     12
01330 #define VIC_CHAN_NUM_RTC     13
01331 #define VIC_CHAN_NUM_EINT0   14
01332 #define VIC_CHAN_NUM_EINT1   15
01333 #define VIC_CHAN_NUM_EINT2   16
01334 #define VIC_CHAN_NUM_EINT3   17
01335 #define VIC_CHAN_NUM_ADC0    18
01336 #define VIC_CHAN_NUM_I2C1    19
01337 #define VIC_CHAN_NUM_BOD     20
01338 #define VIC_CHAN_NUM_Ethernet 21
01339 #define VIC_CHAN_NUM_USB     22
01340 #define VIC_CHAN_NUM_CAN     23
01341 #define VIC_CHAN_NUM_SD_MMC  24
01342 #define VIC_CHAN_NUM_GP_DMA  25
01343 #define VIC_CHAN_NUM_Timer2  26
01344 #define VIC_CHAN_NUM_Timer3  27
01345 #define VIC_CHAN_NUM_UART2   28
01346 #define VIC_CHAN_NUM_UART3   29
01347 #define VIC_CHAN_NUM_I2C2    30
01348 #define VIC_CHAN_NUM_I2S     31
01349 
01350 #define VIC_CHAN_TO_MASK(vctm_chan_num__) (1UL<<vctm_chan_num__)
01351 
01352 #endif  /* __LPC23xx_H */
01353